1. Technical Field
The present invention relates to an interconnection network in a multiprocessor system, and more particularly to an interconnection network in a multiprocessor system utilizing an indirect rotator graph connection method.
2. Related Art
In general, a multiprocessor system includes two or more processors and a communication path for transmitting data between the processors. A memory management and an interconnection network are very important for designing the multiprocessor system. Here, the interconnection network should be designed such that a parallel processing overhead induced by a multiplicity of processors is minimized.
Several variations on multi-degree topologies pertaining to interconnections of multiple processors have been proposed to reduce the longest path between processors and the number of interconnections between processors in order to improve performance and to allow the number of processors to grow larger. These proposals for interconnection topologies of multiple processors are typically shown in the form of a graph in which nodes represent switching points or processing elements and edges represent communication links. Since the topologies tend to be regular, the descriptions lend themselves to graphical displays representing systems. Those skilled in the art readily recognize the conversion of graphical representations of system topologies into hardware. Hence, this shorthand notation is a convenient method of representing larger and more complex hardware multiple-processor systems without the associated complexity of unnecessary details.
Exemplars of recent efforts in the art include U.S. Pat. No. 5,125,076 for a System for Routing Messages in a Vertex Symmetric Network by Using Addresses Formed from Permutations of the Transmission Line Indicees issued to Faber et al., U.S. Pat. No. 4,434,463 for a Multiprocessor Topology with Plural Bases for Directly and Indirectly Coupling Addresses and Relay Stations issued to Quinquis et al., U.S. Pat. No. 5,715,391 for a Modular and Infinity Extendable Three Dimensional Torus Packaging Scheme for Parallel Processing issued to Jackson et al., U.S. Pat. No. 5,689,661 for a Reconfigurable Torus Network Having Switches Between All Adjacent Processor Elements For Statically or Dynamically Splitting The Network Into a Plurality of Subsystems issued to Hayashi et al., U.S. Pat. No. 5,133,073 a Processor Array of N-dimensions Which Is Physically Reconfigurable into N-1 or Fewer Dimensions for issued to Jackson et al., U.S. Pat. No. 5,692,544 for a Massively Parallel Diagonal-fold Tree Array Processor issued to Pechanek et al., U.S. Pat. No. 5,212,773 for a Wormhole Communications Arrangement For Massively Parallel Processor issued to Hillis, U.S. Pat. No. 5,669,008 for a Hierarchical Fat Hypercube Architecture for Parallel Processing Systems issued to Galles et al, U.S. Pat. No. 5,737,628 for a Multiprocessor Computer System with Interleaved Processing Element Nodes issued to Birrittella et al., and U.S. Pat. No. 5,170,482 for an Improved Hypercube Topology for Multiprocessor Computer Systems issued to Shu et al.
While these recent efforts provide advantages, I note that they fail to adequately satisfy a need for an enhanced interconnection network in a multiprocessor system.